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Joint PAPR and Spectrum Sensing in CRNS: A VLSI-Based Approach for Secondary User Integration

In Cognitive Radio Networks (CRNs), Peak-to-Average-Power-Ratio (PAPR) reduction is crucial for mitigating distortion in signals while optimizing spectral efficiency. This work offers a novel strategy for effectively reducing that PAPR in CRN systems, especially when secondary users are incorporated, by utilizing VLSI (Very-Large-Scale Integration) design approaches. The proposed strategy investigates VLSI methods for PAPR reduction, such as Partial-Transmit-Sequence (PTS) techniques. The system is appropriate for CRN applications because it can accomplish real-time PAPR reduction while preserving low power consumption and compact size by implementing these approaches in VLSI hardware. This could entail particular strategies for controlling PAPR with secondary users, such as joint PAPR and spectrum sensing approaches, dynamic power allocation, or user scheduling algorithms. Utilizing the predetermined values of pilot tones, the suggested decoder investigates every possible combination of weighting variables to determine which combination the transmitter has chosen and employed. There appears to be no data rate loss with the proposed decoder since it doesn't require any more pilot tones. This study next gives a digital execution of the described PTS decoder and illustrates its low power qualities, as well as the design and the encoder required at the transmitter to operate the suggested system is being developed using VLSI. The suggested architecture makes it easier for SUs to integrate with CRNs seamlessly. It allows SUs to effectively take advantage of available spectrum opportunities while complying with CRN restrictions and reducing interference with primary users by tackling PAPR and spectrum sensing concurrently. Furthermore, the study discusses the difficulties of incorporating secondary users into CRNs while retaining PAPR management.

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P. Shanmuga Sundaram mail -
M. Vasanthi mail -
P. Sangeetha mail
link https://doi.org/10.54216/JCHCI.090102

Volume & Issue

Vol. Volume 9 / Iss. Issue 1

Details open_in_new

Classification Segmentation and Visualization of Intracranial Hemorrhage in CT Brain Images

Intracranial hemorrhage (ICH) poses a large chance to affected person fitness, regularly modern requiring set off diagnosis and intervention. In latest years, the medical imaging techniques, specifically computed tomography (CT) scanning, have end up critical tools for detecting and characterizing ICH. This paper offers a complete evaluate comprehensive review of the state-of-the-art techniques for the segmentation, category, and visualization cutting-edge intracranial hemorrhage in CT mind pics. The evaluate encompasses numerous methodologies, consisting of conventional picture processing strategies, system cutting-edge algorithms, and deep brand new strategies, highlighting their strengths, limitations, and capability applications in scientific exercise. Additionally, it discusses the challenges associated with correct ICH detection and quantification, inclusive of the presence modern day artifacts, anatomical variations, and sophistication imbalance. Furthermore, the paper explores emerging tendencies in ICH research, which includes the combination trendy multimodal imaging information and the improvement trendy interactive visualization gear for enhanced medical choice-making. The segmented portion from each CT image is constructed into a single 3D volumetric structure and essential information such as region Area, volume and location are provided. Further the classification accuracy between normal brain and ICH brain is 95.8%. Such a 3D visualization, Classification and volumetric analysis of ICH can provide the exact and necessary information to the neurologist which is essential for the treatment of ICH.

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K. Rajesh mail -
A. Silambarasan mail -
R. Hemalatha mail -
E. Sharmila mail
link https://doi.org/10.54216/JCHCI.090103

Volume & Issue

Vol. Volume 9 / Iss. Issue 1

Details open_in_new

Optimizing accuracy rate of Detection of COVID-19: A Machine Learning approach

COVID-19, one of the most highly transmissible diseases in the twenty-first century, has had a profound impact on global lifestyles. Recently, the medical industry has increasingly relied on machine learning, which shows promise in anticipating the presence of COVID-19. By using machine learning techniques, test result turnaround time can be accelerated, and medical personnel can promptly attend to patients' needs. These algorithms analyze various attributes to classify COVID patients and predict their likelihood of contracting the disease. This study aims to utilize X-ray images processed by machine learning algorithms to predict the occurrence of COVID-19 and enhance its detection rate. The paper outlines two strategies employing machine learning techniques: one for predicting the likelihood of infection and the other for identifying positive cases. Different machine learning algorithms, such as decision trees, logistic regression, support vector machines, naive Bayes, and artificial neural networks, were employed. The simulation results reveal that the artificial neural networks model outperforms other methods in terms of accuracy rate.

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K. Selvi mail -
K. Muthumanickam mail -
P. Vijayalakshmi mail -
S. Sakthivel mail
link https://doi.org/10.54216/JAIM.090101

Volume & Issue

Vol. Volume 9 / Iss. Issue 1

Details open_in_new

VLSI Implementation of AES Block Cipher Based Data Hiding in Image Processing

A common symmetric key block cypher for protecting electronic data is called the Advanced Encryption Standard (AES). The implementation of the AES algorithm using Very-Large-Scale Integration (VLSI) is examined in this study. Cryptographic algorithms can be realised in hardware thanks to VLSI, which has advantages over software implementations in terms of increased processing speed and security. In this work, an AES block cypher core designed and implemented with VLSI techniques is described. We investigate various architectural designs to maximise performance indicators such as area, power consumption, and throughput. The trade-offs between different implementation options and design concerns for important components such as S-boxes will be covered. To illustrate the performance and usefulness of the implemented AES core, simulation results will be given. This paper examines the VLSI implementation of the Advanced Encryption Standard (AES), with a focus on image processing applications, even though it is essential for general data security. Effective on-chip encryption and decryption can be included into image processing systems by implementing the AES algorithm into specialised hardware circuits. Benefits of this VLSI design include enhanced performance over software-based solutions on resource-constrained image processing devices, the ability to encrypt images in real-time for secure transmission or storage, and the potential for reduced power usage for battery-powered applications.

groups
Kumarganesh S. mail -
Socratees P. mail -
Rajamanickam G. mail
link https://doi.org/10.54216/IJWAC.090101

Volume & Issue

Vol. Volume 9 / Iss. Issue 1

Details open_in_new

Performance Optimization of Transmission Gate-Based D Flip-Flop using Clock Gating Technique

This work investigates into the meticulous analysis of the Transmission Gate (TG) based D Flip-Flop integrated with dynamic XOR-based clock gating, aimed at analyzing power consumption patterns and potential power savings across varying frequencies. While power consumption inherently reduces with smaller technology nodes, but this work demonstrates that dynamic clock gating can achieve further power savings, especially at higher operational frequencies and lower data activity. The outcomes represent a deeper understanding of power optimization techniques for sequential circuits. The analysis is performed using Cadence Virtuoso in a 90nm technology process, which determine the sophisticated interaction between design elements and power dynamics. Through comprehensive simulations, the power consumption of TG-based D flip-flops is meticulously examined across diverse technology nodes. Furthermore, the efficacy of integrating dynamic XOR-based clock gating to this flip-flop design is explored, unveiling its potential to yield substantial power savings. The research underscores the multifaceted nature of low-power design strategies, emphasizing their relevance across various hierarchies including system, architecture, circuit, and device levels. While advancements in technology nodes naturally lead to reduced power dissipation, this study illuminates the additional power-saving opportunities presented by the dynamic XOR-based clock gating approach. Especially, in this investigation highlights the significance of this approach particularly in scenarios characterized by higher frequencies of operation and low data activity. By leveraging dynamic XOR-based clock gating, the research showcases how power efficiency can be further augmented, offering insights into enhancing the overall energy efficiency of digital systems. In summary, this project provides a nuanced understanding of power dynamics in TG-based D flip-flops, shedding light on the intricate balance between technology advancements and innovative design methodologies for achieving optimal power efficiency. Through meticulous analysis and simulation, it unveils a promising avenue for realizing significant power savings, thereby contributing to the advancement of low-power design paradigms in modern digital systems.

groups
Tamilselvan A. mail -
Devika T. mail -
Anitha S. mail
link https://doi.org/10.54216/IJWAC.090102

Volume & Issue

Vol. Volume 9 / Iss. Issue 1

Details open_in_new

Cooperative Spectrum Sensing Architecture for Energy-Efficient Data-Fusion-Based Cognitive Radio Network

This demand can be satisfied by cognitive radio (CR) technology thanks to the growing desire to utilize existing radio frequency bands more effectively. This paper suggests a hardware-efficient, very-large spectrum sensor. In cooperative cognitive radio networks, data fusion is not provided by a new-scale integration (VLSI) architecture. The cooperative method to spectrum sensing and management as a proposed concept uses approaches for data fusion to address the difficulties. Our VLSI system delivers high throughput with exceptional performance by combining the latest sensing algorithms with an effective hardware architecture. The overall performance of the spectrum and spectrum awareness are enhanced by the cooperative theoretical radio communication system. In order to enable the network to make judgements that can be modified utilizing combined data from scattered spectrum sensors, the study examines the integration of network fusion techniques. The suggested scheme's primary characteristics are its hardware efficiency, low power consumption, and real-time flexibility for changing spectrum conditions. Through simulations and comparison with existing methods, it is assessed. System performance is tracked, and the results indicate that faster and more accurate spectrum sensing is required in order to apply notions of spectrum sharing that make sense.

groups
Premkumar S. mail -
D. Israel -
S. Veerakumar mail -
T. Praveenkumar
link https://doi.org/10.54216/IJWAC.090103

Volume & Issue

Vol. Volume 9 / Iss. Issue 1

Details open_in_new

Smart Accident Detection using IoT Technology

Road accidents and emergency services delay are the main significant issues. To overcome these issues need to develop a system. Efficient handling of accidents through the immediate detection and provide timely aid are more crucial. Accident detection and emergency system depends on IoT (Internet of things) with minimum delay are gaining significant attention towards industry and academic literature. Several researches are investigated using IOT technology to detect accidents. In this work, we proposed an effective accident detection method by employing five sensors not only to detect accident but also to report type of accident such as collision, no accident, roll over or fall off. In addition to that, the status of the accident is communicated to the IBM Watson Cloud platform. The incoming data received in the node red platform is integrated with the Google Maps to show location and other information about the accident that can be accessed by the hospital through website and also sending alert messages to victim acquaintances. In addition, two Machine Learning (ML) models based on K-Nearest Neighbor (KNN) model and the Naïve Bayes (NB) model are compared to find out the best accident detection model. It is noticed that the KNN model is the very effective ML model, which employed to know the accident status and also to enhance the system by providing patient’s details, a kill switch and sending messages often till acknowledgement is received.

groups
Sindhuja M. mail -
Vijay Murugan S. mail -
Elarmathi S. mail
link https://doi.org/10.54216/IJWAC.090104

Volume & Issue

Vol. Volume 9 / Iss. Issue 1

Details open_in_new

Efficacious Framework for The Detection of Link Flooding Attack in Mobile Ad Hoc Network

A novel honey pot deception trace back model, or honey pot IDS, is offered. The system is located on the server, which is the site of network intrusion deceptions. From there, it keeps an eye on all incoming traffic and uses nodes that carry out network weight age studies to continuously weigh the data. For every client connected to the server, it serves as a construct to look at the packet analysis and transmission path to which the IP processed the intrusion detection system. This LF-IDS detects intrusions using both anomaly-based and rule-based intrusion detection methods. By gathering and examining the packets from incoming traffic, the system initially collects data on the packet agent monitoring system. The trespasser is led to a honey pot that will be constructed as a mitigation site.

groups
M. Gautham mail -
D. Chitra mail -
B. Samitha
link https://doi.org/10.54216/IJWAC.090105

Volume & Issue

Vol. Volume 9 / Iss. Issue 1

Details open_in_new

Blockchain-Enabled Multi-Head Attention Based Deep Learning Model for Intrusion Detection System in Smart Networks

Intrusion Detection Systems (IDS) are increasingly being integrated into smart homes for effective pervasive sensing and resource management, thanks to advancements in sensor technologies and the development of Information and Communication Technology (ICT). Securing IDSs in smart homes is significant for safeguarding crucial data and ensure the integrity of related devices. Implementing strong cybersecurity, measures, including regular software updates, encrypted communication protocols, and secure authentication mechanisms, is critical to safeguard potential risks. As the smart home network constantly increasing, developers, users, and manufacturers must work together to maintain and prioritize stringent security standards, alleviating the risks closely related to connected devices and preserving the safety and privacy of the consumer. Blockchain (BC) technology can increase the security of IDS in smart homes by giving a tamper-resistant and decentralized framework to manage data transactions and device interactions. By leveraging blockchain, smart home networks can establish a more secure and resilient infrastructure, which provides consumers with high confidence in the security and privacy of the interconnected devices. This study introduces a Blockchain and Multi-Head Attention-Based Deep Learning for Intrusion Detection System in Smart Networks (BCMHDL-IDSSN) technique in Smart Home Networks. The BCMHDL-IDSSN method aims to enhance security in the smart home networks. In the BCMHDL-IDSSN technique, BC technology is used to achieve security. Besides, the BCMHDL-IDSSN technique involves the design of a multi-head attention bidirectional gated recurrent unit (MHA-BiGRU) method for the detection of malicious activities. Finally, an enhanced pigeon-inspired optimization (EPIO) model is applied for the optimal hyperactive parameter choice of the MHA-BiGRU model. A detailed investigation was applied to validate the performance of the BCMHDL-IDSSN method. The simulation values emphasized that the BCMHDL-IDSSN method gains high efficiency over other techniques.

groups
Ehab Bahaudien Ashary mail
link https://doi.org/10.54216/JISIoT.150201

Volume & Issue

Vol. Volume 15 / Iss. Issue 2

Details open_in_new

Design and implementation of intelligent home data cloud storage system with large system and big data

The increasing maturity of 5G technology and Internet of Things technology makes people feel the convenience brought by high-tech in their daily lives, and smart homes gradually penetrate into people’s lives. Aiming at the disadvantages of traditional data storage such as low flexibility and slow speed, an effective cloud storage system for data storage and management is designed. Through the design of the data cloud storage system structure and database, and the hardware design of the smart home data cloud storage system, this paper provides users with various functions, verifies the practicability of the cloud storage system through system testing and analysis, and improves the functions of the smart home data cloud storage system.

groups
Yangxia Shu mail -
Hai Liu mail
link https://doi.org/10.54216/JISIoT.150202

Volume & Issue

Vol. Volume 15 / Iss. Issue 2

Details open_in_new